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ADVANCED TECHNICAL INFORMATION
HiPerFET TM MOSFET
ISOPLUS220 TM
Electrically Isolated Back Surface
N-Channel Enhancement Mode
High dv/dt, Low t rr , HDMOS TM Family
IXFC13N50
V DSS
I D25
R DS(on)
t rr
= 500
= 12
= 0.4
≤ 250
V
A
?
ns
ISOPLUS 220 TM
Symbol
Test Conditions
Maximum Ratings
V DSS
T J = 25 ° C to 150 ° C
500
V
V DGR
V GS
V GSM
T J = 25 ° C to 150 ° C; R GS = 1 M ?
Continuous
Transient
500
± 20
± 30
V
V
V
G
D
S
Isolated back surface*
I D25
I DM
T C = 25 ° C
T C = 25 ° C, pulse width limited by T JM
12
48
A
A
G = Gate
S = Source
D = Drain
I AR
E AR
dv/dt
P D
T J
T JM
T stg
T L
Weight
T C = 25 ° C
T C = 25 ° C
I S ≤ I DM , di/dt ≤ 100 A/ μ s, V DD ≤ V DSS ,
T J ≤ 150 ° C, R G = 2 ?
T C = 25 ° C
1.6 mm (0.062 in.) from case for 10 s
13
18
5
140
-55 ... +150
150
-55 ... +150
300
3
A
mJ
V/ns
W
° C
° C
° C
° C
g
Features
Silicon chip on Direct-Copper-Bond
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
Low drain to tab capacitance(<35pF)
Low R DS (on) HDMOS TM process
Rugged polysilicon gate cell structure
Unclamped Inductive Switching (UIS)
rated
FastintrinsicRectifier
Applications
DC-DC converters
Battery chargers
Symbol
Test Conditions
Characteristic Values
(T J = 25 ° C, unless otherwise specified)
min. typ. max.
Switched-mode and resonant-mode
power supplies
DC choppers
AC motor control
V DSS
V GS = 0 V, I D = 250 μ A
500
V
Advantages
V GS(th)
I GSS
I DSS
R DS(on)
V DS = V GS , I D = 2.5 mA
V GS = ± 20 V DC , V DS = 0
V DS = 0.8 ? V DSS
V GS = 0 V
V GS = 10 V, I D = I T
Notes 1, 2
T J = 25 ° C
T J = 125 ° C
2
4
± 100
200
1
0.4
V
nA
μ A
mA
?
Easy assembly: no screws or isolation
foils required
Space savings
High power density
Low collector capacitance to ground
(low EMI)
See IXFH13N50 data sheet for
characteristic curves
? 2003 IXYS All rights reserved
DS98756(7/03)
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